Power consumption is increasingly a subject of concern to integrated circuit designers. Accurate prediction of an integrated circuit's power consumption is important for selection of the proper packaging for the integrated circuit, battery life prediction when the circuit is to be used in a portable or other battery powered device, and chip lifetime prediction. In addition, power consumption prediction can be used to determine the type of heat sink resources needed, if any, for an integrated circuit, since uncompensated thermal effects can lead to performance degradation and chip failure.
Power consumption predictions are also important for designing a proper power distribution network within an integrated circuit. For instance, power busses for an integrated circuit must be sized so as to be able to handle both average and peak current densities, and also to provide sufficient voltage levels to those circuits farthest from the power bus. A power bus, or a power strap to a particular module or section of an integrated circuit may be sufficiently large to handle the maximum sustained power usage expected of a chip, thereby providing sufficient voltage for operation of all portions of the circuit and preventing the power bus from being damaged or destroyed by the buildup of excess heat, while still being insufficiently large to prevent metal migration caused by short current spikes. Thus, it is important to accurately predict both average and peak current usage by an entire integrated circuit and also by portions of the integrated circuit having separate power straps.
Power consumption occurs dynamically (AC)--resulting from the switching of a signal from one voltage level to another, and statically (DC)--when the circuit is "quiet" due to pullups and pulldowns, level shifters, and leakage currents. Most dynamic power consumption is the result of charging and discharging of capacitances in the circuit. Capacitances include pin capacitances, transistor capacitances, and interconnect capacitances. The amount of power consumed by capacitance charging and discharging is represented by the following equation: EQU Power=Capacitance.times.Voltage-Swing.sup.2 .times.Frequency
Dynamic power consumption is also caused by short circuit current, such as the short circuit current that occurs in CMOS inverters for slow ramp signals.
Prior to the present invention, power consumption simulation methods have generally used either (A) power consumption models based upon average switching frequency estimate formulas and prototype evaluation, and (B) analog circuit simulation techniques. Power consumption simulations based upon average switching frequency estimate formulas and prototype evaluation can be used to estimate the power usage of large circuits, but are too inaccurate to be used as the basis for designing an integrated circuit's power network or to accurately analyze tradeoffs (e.g., power usage, speed, and circuit size tradeoffs) between alternate circuit designs. Analog circuit simulation techniques used to determine power usage by proposed circuits are very accurate but use so much computer resources that the simulation of large circuits with hundreds of thousands of logic gates is either impossible or impractical.
A prior logic circuit simulator by Compass, QSIM, included an "unreleased" version of a power simulator, which assigned an average power usage value to each input and output port of each circuit cell, and then during simulation of the operation of the circuit posted a power usage of the assigned amount whenever a signal transition was determined to have occurred on each cell input port. Thus, the prior QSIM power simulation product computed power usage without taking into account the slew rate of the signal on a cell's input port, the logic state of the cell and static power usage. This prior QSIM power simulation product accumulated total power usage for a specified simulation time, but did not provide the tools necessary to detect peak power usage, to perform hierarchical power analyses, and other power usage analyses desired by circuit designers.
It is a goal of the present invention to provide an accurate integrated circuit power consumption analysis tool to provide the designers of ASICs the information needed to make well informed design decisions and evaluate trade-offs.
It is another goal of the present invention to be able to accurately model the power usage of entire submicron ASIC designs having 200,000 logic gates and more.
Another goal of the present invention is to provide a hierarchical analysis capability, allowing the evaluation of power bus widths, design partitioning, clock gating strategies, asynchronous designs, and power bus gating to circuit blocks.
Another goal of the present invention is to provide both AC and DC power consumption analysis, average and peak power consumption analyses, analyses of the dependency of power consumption on input slew rates, output loads, power supply level and temperature, and to provide best, typical and worst case power consumption analyses.
Yet another goal of the present invention is to provide power consumption analyses with simulation execution speeds significantly better than would be possible using an analog circuit simulator.
Finally, it is a goal of the present invention to support the power usage simulation of integrated circuits having multiple power supplies, and to support power usage simulation of integrated circuits using both gate array designs and cell based designs.